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- W4385187177 abstract "With the proliferation of embedded computing, many machine learning (ML) applications have found their way into embedded devices. The SVM classifier is deemed suitable for real-world ML applications, which often comprise large-scale multi-dimensional data. In this paper, we introduce an FPGA-based systolic array architecture to support and accelerate SVM classifier on resource-constrained embedded devices. We also introduce a unique system-level architecture to further enhance speedup and to facilitate real-time processing. Our systolic array achieves a maximum speedup of 107x compared to its software counterparts, and a maximum classification accuracy of 98.5%." @default.
- W4385187177 created "2023-07-25" @default.
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- W4385187177 date "2023-05-21" @default.
- W4385187177 modified "2023-09-23" @default.
- W4385187177 title "A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices" @default.
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- W4385187177 doi "https://doi.org/10.1109/iscas46773.2023.10182159" @default.
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