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• W4385192446 abstract "A 210 + WL layers 1Tb 3b/cell 3D-Flash Memory achieves the high bit density of $gt17$ Gb/mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . Physical 8plane architecture realizes low read latency of 40us and high program throughput of 205MB. High interface speed of 3.2Gbps is accomplished by reducing DQ area in the X direction to 41%. Hybrid row address decoders (X-DEC) can deal with the wiring congestion issue caused by the new architecture, minimizing the read latency degradation. One-pulse-two-strobe technique reduces sensing time by 18% and contributes to the achievement of 205MB/s program throughput." @default.
• W4385192446 created "2023-07-25" @default.
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• W4385192446 date "2023-06-11" @default.
• W4385192446 modified "2023-10-03" @default.
• W4385192446 title "A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm² bit density with 3.2Gbps interface and 205MB/s program throughput" @default.
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• W4385192446 doi "https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185237" @default.
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