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• W4385192512 abstract "For the past decades, the density of DRAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond the 10 nm process node increasingly poses process and reliability challenges. As Flash technology made a pivotal and successful innovation via 3D NAND, DRAM technology may also adopt vertical stacking memory cells. Vertically stacked DRAM (VS-DRAM) continues to increase bit density on a die by increasing the number of layers along with reducing the size of the transistor. In this paper, the opportunities and challenges of VS-DRAM are discussed." @default.
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• W4385192512 date "2023-06-11" @default.
• W4385192512 modified "2023-10-16" @default.
• W4385192512 title "Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -" @default.
• W4385192512 cites W3003352156 @default.
• W4385192512 doi "https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185290" @default.
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