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- W4385613937 abstract "With the improvement of semiconductor, MOSFET devices are becoming smaller, making devices more sensitive to ESD. Therefore, the ESD research of MOSFET devices becomes more important. Simulation research can reduce the huge cost caused by the test, which plays an important role in ESD protection design. Based on Electrostatic Discharge (ESD) failure mechanism of MOSFET, the destructive and potential failure mechanism of deep submicron NMOSFET under Transmission Line Pulse (TLP) stress are simulated in this paper. The simulation analysis shows that the destructive failure of the device is caused by the breakdown of the oxide layer between the gate and drain due to the very strong electric field triggered by ESD action. Moreover, even if ESD is lower than the failure voltage threshold, multiple actions can also cause device failure. At the same time, the simulation shows that the abnormal charge state of the oxide layer caused by hot carrier injection is an important reason for the potential failure of the device, and the cumulative effect of ESD on the threshold voltage of the device is huge. The simulation study provides a reference for the future application of TLP test technology in simulation research." @default.
- W4385613937 created "2023-08-07" @default.
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- W4385613937 date "2023-08-07" @default.
- W4385613937 modified "2023-09-22" @default.
- W4385613937 title "Simulation of deep submicron MOSFET failure characteristics under ESD stress" @default.
- W4385613937 cites W2324362018 @default.
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- W4385613937 doi "https://doi.org/10.1117/12.2687097" @default.
- W4385613937 hasPublicationYear "2023" @default.
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