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• W4385730899 abstract "Thanks to the high energy efficiency achieved by approximate circuits, the exploration of approximate solutions for a wide of applications is the focus of academic and industrial research. However, defining the most appropriate approximation considering the power consumption and accuracy trade-off can be exhaustive. This paper proposes a novel approach to estimate the synthesis results for approximate adders (AxA) with different bit-width and approximation levels based on a database and simple mathematical operations to reduce the synthesis process complexity during an approximate circuit development. We implement the proposed approach to estimate the synthesis results for the Copy, Error-Tolerant Adder I (ETA-I), Lower-part-or (LOA), and Truncation (Trunc) AxAs. Comparing our estimation with real synthesis results obtained by an industrial synthesis tool, we prove the approach’s efficiency by presenting an average error on the estimated parameters (area, power and delay) less than 10% in the worst case. In addition, our approach reduces by more than 25 times the number of synthesis runs when estimating the synthesis results for all circuits in the bit width range of 2 to 64 with all possible approximation levels." @default.
• W4385730899 created "2023-08-11" @default.
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• W4385730899 date "2023-06-01" @default.
• W4385730899 modified "2023-10-18" @default.
• W4385730899 title "AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation." @default.
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• W4385730899 doi "https://doi.org/10.1109/dsn-w58399.2023.00051" @default.
• W4385730899 hasPublicationYear "2023" @default.
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