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- W4386014780 abstract "Recently, the histogram estimation architectures for analyzing the sampled data have numerous applications in image processing, communications, computer vision, and pattern recognition. In this work, the proposed histogram estimation structure is used to count up the bin values, and also the structure is implemented on Field Programmable Gate Array (FPGA) and also on Application Specific Integrated Circuit (ASIC) platform. The input 8 × 8 image is transformed into binary samples by using MATLAB, and these values are given to the input of Verilog code. The simulation results of the proposed architecture are obtained from the ModelSim software. In this we analyze the performance of both existed and proposed structures for 8 × 8 image and to obtain the performance of ASIC and are implemented in cadence encounter digital IC implementation with 180 nm technology and the percentage decrease of power, delay, and area is 32%, 18%, and 17.6%. And also, the utilization of look up tables, slice registers, and number of flip-flops is reduced for Virtex-6 device." @default.
- W4386014780 created "2023-08-21" @default.
- W4386014780 creator A5029191753 @default.
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- W4386014780 date "2023-01-01" @default.
- W4386014780 modified "2023-10-02" @default.
- W4386014780 title "Design and Implementation of Histogram Estimation Architectures for 8 × 8 Image" @default.
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- W4386014780 doi "https://doi.org/10.1007/978-981-99-3691-5_23" @default.
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