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- W4386227046 abstract "Spiking Neural Networks (SNNs) are becoming increasingly popular for their application in Edge Artificial Intelligence (Edge-AI) due to their sparse and low-latency computation. Among these networks, analog hardware SNNs are chosen for their ability to emulate complex dynamics in neurons and synapses, especially in integrated Metal Oxide Semiconductor (MOS) technology. They can form memories of external stimuli by modulating the strength of synaptic weights. In this context, binary weights are a common hardware design choice, due to their ease to program and store. The use of binary weights in SNNs worsens the bias introduced by the coding level of input stimuli (i.e. fraction of active input nodes), where the network activity is highly correlated to the number of excited neurons. In this paper, we present a Complementary Metal Oxide Semiconductor (CMOS) solution for the coding level bias, by proposing a novel circuit that employs synaptic normalisation at the neuron level. This circuit modifies the gain of the neuron depending on its input weights, with a small footprint and therefore high scalability." @default.
- W4386227046 created "2023-08-29" @default.
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- W4386227046 date "2023-08-01" @default.
- W4386227046 modified "2023-10-15" @default.
- W4386227046 title "Synaptic Normalisation for On-Chip Learning in Analog CMOS Spiking Neural Networks" @default.
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- W4386227046 doi "https://doi.org/10.1145/3589737.3606007" @default.
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