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- W4386275792 abstract "As manycore processors grow larger, Networks-on-chips (NoCs) have become the standard on-chip interconnect solution. However, industrial NoCs, unlike early academic proposals, comprise multiple physical layers with inter-dependencies that affect performance. Existing techniques fail to capture this critical interaction as they focus on a single layer NoC. This paper presents a performance analysis technique that models the interaction and estimates the destination layer’s blocking probability to compute finite queuing delays in the source layer. Our experimental evaluations show our approach is always within 10% of, and five times faster than, cycle-accurate simulations for 6×6 mesh NoCs with synthetic and real traffic." @default.
- W4386275792 created "2023-08-31" @default.
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- W4386275792 date "2023-01-01" @default.
- W4386275792 modified "2023-09-30" @default.
- W4386275792 title "Fast Analysis using Finite Queuing Model for multi-layer NoCs" @default.
- W4386275792 doi "https://doi.org/10.1109/mdat.2023.3310167" @default.
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