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- W4386323377 abstract "To realize high speed processing of parallel applications in high-end IoT devices, multi or many core processors are implemented on a VLSI chip. As the interconnection system of many core processors (nodes), Network-on-Chip (NoC) is attracted attention. In NoC, fault-tolerant routing plays an important role in communication between nodes. Many fault-tolerant routing methods have been studied and evaluated mainly in terms of communication performance. However, the evaluation of only communication performance is not sufficient; it is also necessary to evaluate execution time of parallel applications. We evaluated execution time of parallel applications for four fault-tolerant routing methods. We used parallel tasks generated by TGFF, and employed a genetic algorithm to obtain semi-optimal task mapping. Simulation result shows that the fault-tolerant routing method called Passage reduced application execution time by about 11%, compared with the method called Fcube4." @default.
- W4386323377 created "2023-09-01" @default.
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- W4386323377 date "2023-07-17" @default.
- W4386323377 modified "2023-09-28" @default.
- W4386323377 title "Performance Evaluation of Parallel Tasks for Fault-tolerant Routing Methods" @default.
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- W4386323377 doi "https://doi.org/10.1109/icce-taiwan58799.2023.10226850" @default.
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