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- W4386494908 abstract "Severe path-loss and small wavelength makes the D-band (110–170 GHz) antenna design, fabrication, integration and measurement challenging. This paper presents a novel antenna design using a single-layer printed circuit board (PCB) process. By optimizing unequal antenna row spacing, row-to-row shift and different unit-cell parameters, the proposed patch antenna array is capable of 45-degree slant polarization. The designed impedance/length matching components can support both wire-bonding and flip-chip antenna integration techniques, which are compatible with different chip pitch dimensions. The boresight realized gain of a 32-channel array is 26.7 dBi at 140 GHz with a 3-dB realized gain bandwidth from 136.5 to 146.4 GHz. The simulated scanning range is <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$pm 45^{circ}$</tex> . Therefore, the proposed antenna array maintains high gain, wide gain bandwidth and moderate beam steering angle with low-cost, low-complexity and easy fabrication." @default.
- W4386494908 created "2023-09-07" @default.
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- W4386494908 date "2023-07-23" @default.
- W4386494908 modified "2023-10-16" @default.
- W4386494908 title "A D-band Low-cost High-gain Phased Antenna Array for 6G Applications" @default.
- W4386494908 cites W3128279830 @default.
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- W4386494908 doi "https://doi.org/10.1109/usnc-ursi52151.2023.10238184" @default.
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