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- W4386746087 abstract "Partial Reconfiguration (PR) is a key technique in the application design on modern FPGAs. However, current PR tools heavily rely on the developer to manually conduct PR module definition, floorplanning, and flow control at a low level. The existing PR tools do not consider High-Level-Synthesis languages either, which are of great interest to software developers. We propose HiPR, an open-source framework, to bridge the gap between HLS and PR. HiPR allows the developer to define partially reconfigurable C/C++ functions, instead of Verilog modules, to accelerate the FPGA incremental compilation and automate the flow from C/C++ to bitstreams. We use a lightweight Simulated Annealing floorplanner and show that it can produce high-quality PR floorplans an order of magnitude faster than analytic methods. By mapping Rosetta HLS benchmarks, we demonstrate that the incremental compilation can be accelerated by 3–10 × compared with state-of-the-art Xilinx Vitis flow without performance loss, at the cost of 15-67% one-time overlay set-up time." @default.
- W4386746087 created "2023-09-15" @default.
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- W4386746087 date "2023-09-14" @default.
- W4386746087 modified "2023-09-26" @default.
- W4386746087 title "ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation" @default.
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- W4386746087 doi "https://doi.org/10.1145/3617837" @default.
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