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- W4386768211 abstract "At the cusp of technology scaling venturing into the nanometer scale, sub-micron devices are bound to encounter technology issues such as increased leakage currents, unwarranted on-current ratio, reliability issues, and varying manufacturing cost. Consequent to addressing novel improvements and innovations in CMOS device modeling and research, various new nanoelectronics devices are actively being investigated to augment or in a way mitigate the aforesaid bottlenecks in conventional CMOS devices. While such sub-micron devices offer ultra-high density system integration, they are still facing reliability and repeatability challenges. Unlike conventional MOSFETs, junction-less field-effect transistors (JLFETs) contain no metallurgical junctions, so they are simpler to process and less costly to manufacture. JLFETs utilize a gated semiconductor film to control the current flowing through it. In this paper, the short channel effects (SCEs) of a JL double-gate metal-oxide-semiconductor field effect transistor (JL DGMOSFET) have been studied in detail using Silvaco Atlas 2-D simulator in terms of drain-induced barrier lowering (DIBL) effect, slope of the subthreshold, mobility degradation, and current density. A comparison with symmetric conventional double-gate (DG) MOSFET has been made to highlight the importance of JL MOSFET. It is observed that use of high-k dielectric material as an insulator not only improves the (ION/IOFF) ratio, lowers the threshold voltage but also reduces the subthreshold swing and improves mobility due to better control of the gate over channel." @default.
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- W4386768211 date "2023-01-01" @default.
- W4386768211 modified "2023-10-17" @default.
- W4386768211 title "Analysis of Short Channel Effects in Symmetric Junction-Less Double-Gate Doped MOSFET Using Atlas 2-D Simulator" @default.
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- W4386768211 doi "https://doi.org/10.1007/978-981-99-4175-9_50" @default.
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