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- W4386952600 abstract "This paper presents a design of a highly scalable and precise current-mode winner-take-all circuit with digital address generation. The design is based on current mirrors and comparators that use the cross-coupled latch structure. The circuit implementation using a 45 nm CMOS process is presented. Experiments are presented considering the hardware implementation of deep neural networks for classification using various datasets, which demonstrate that the proposed design is 100% accurate in selecting the winner." @default.
- W4386952600 created "2023-09-23" @default.
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- W4386952600 date "2023-09-05" @default.
- W4386952600 modified "2023-10-05" @default.
- W4386952600 title "High Precision Winner-Take-All Circuit for Neural Networks" @default.
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- W4386952600 doi "https://doi.org/10.1109/socc58585.2023.10256761" @default.
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