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- W4387103936 abstract "<p>This article presents a Hardware-Software (HWSW) Interface for Error Logging and Reporting, whose aim is to improve Reliability, Availability, and Serviceability (RAS) in both 32- and 64-bit RISC-V architectures. A HW-SW Interface defines the facilities by which detected hardware errors are logged into an ad hoc set of registers (i.e., error records) and then reported to system software. This way, system software can access the errorrelated information stored in the error records and takes actions to recover from hardware errors. The developed architecture has been firstly synthesized on both FPGA (Xilinx UltraScale+ MPSoC) and Standard-Cell technologies (45nm and 7nm libraries). The synthesis results have been reported and discussed, but no comparison with the state-of-the-art was made since this is the first public work targeting design and implementation of a HW-SW Interface for Error Logging and Reporting. Then, the architecture has been implemented and validated within a test System-on-Chip (SoC), on FPGA, featuring the RISCV CV32E40P core. The proposed HW-SW Interface provides the feature of Error Logging and Reporting for generic RISC-V architecture. In addition, it offers a significant degree of flexibility and configurability to effectively satisfy the needs of different application scenarios by selectively incorporating or removing specific features.</p>" @default.
- W4387103936 created "2023-09-28" @default.
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- W4387103936 date "2023-09-27" @default.
- W4387103936 modified "2023-09-28" @default.
- W4387103936 title "HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS in RISC-V Architectures" @default.
- W4387103936 doi "https://doi.org/10.36227/techrxiv.24179745.v1" @default.
- W4387103936 hasPublicationYear "2023" @default.
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