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• W4387251589 abstract "Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</inf> scaling with optimal V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</inf> (T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions." @default.
• W4387251589 created "2023-10-03" @default.
• W4387251589 creator A5009612340 @default.
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• W4387251589 date "2023-09-11" @default.
• W4387251589 modified "2023-10-18" @default.
• W4387251589 title "MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization" @default.
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• W4387251589 doi "https://doi.org/10.1109/essderc59256.2023.10268514" @default.
• W4387251589 hasPublicationYear "2023" @default.
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