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- W4387319229 abstract "Existing estimation-based approaches or predictive algorithm-based approaches use additional sensing circuits and complex calculations to implement digital average current mode control (ACMC). Uniformly sampled digital ACMC techniques either use dual-edge modulation or leading-edge modulation for sampling the average inductor current. However, they cannot be configured for trailing-edge modulation. This paper proposes a sampling mechanism to implement digital ACMC in a boost converter under trailing-edge modulation. The proposed sampling mechanism is simple and cost-effective as it does not need any additional sensing circuits or fast analog-to-digital converters (ADCs). Furthermore, the proposed mechanism is insensitive to system’s parasitics and parameter variations. The mechanism can be easily configured for leading-edge modulation. Discrete-time modeling technique is considered for small-signal modeling and controller design. The proposed sampling mechanism is implemented on an FPGA platform to control an in-house boost converter prototype. The proposed technique can be easily extended for other digital average current mode controlled converters." @default.
- W4387319229 created "2023-10-04" @default.
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- W4387319229 date "2023-01-01" @default.
- W4387319229 modified "2023-10-05" @default.
- W4387319229 title "An Event-driven Sampling Mechanism for Digital Average Current-mode Controlled Boost Converter" @default.
- W4387319229 doi "https://doi.org/10.1109/tcsii.2023.3321890" @default.
- W4387319229 hasPublicationYear "2023" @default.
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