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- W4387409473 abstract "This is one of several articles in a special volume devoted to micro-electronics in the field of High Energy Particle Physics, reviewing readout integrated circuits for hybrid pixel detectors. The article classifies circuits into generations according to technology and features, and discuses the general evolution of circuit architecture and innovations, in particular related to track reconstruction in high rate and radiation environments, up to 3 GHz/cm2 and 1 Grad, respectively. 21 Different chips are compared, most of them used in LHC experiments, with number of pixels per chip ranging from 50 to 150 000, and chip sizes ranging from 0.5 cm2 to 4 cm2. The first generation of chips used in LHC experiments were built using 0.25μm CMOS feature size, while the present, third generation of chips is based on 65 nm CMOS. Readout architecture, layout, analog performance including large chip effects, data transmission, and powering are discussed. Radiation tolerance issues pertaining to this application are summarized, as integrated circuit radiation tolerance is covered in a dedicated article." @default.
- W4387409473 created "2023-10-07" @default.
- W4387409473 creator A5023252694 @default.
- W4387409473 date "2023-10-01" @default.
- W4387409473 modified "2023-10-08" @default.
- W4387409473 title "Hybrid pixel readout integrated circuits" @default.
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- W4387409473 doi "https://doi.org/10.1016/j.nima.2023.168725" @default.
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