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- W4387411191 abstract "This paper proposes an advanced electrical impedance tomography (EIT) imaging IC that is designed to enhance stability against contact impedance variations. The 6 m$mathrm{m}^{2}$ chip is fabricated using a TSMC 180 nm CMOS process and contains 2 key features: 1) a high input impedance instrumentation amplifier (IA) with auxiliary source followers for robust voltage sensing, and 2) a Trans-Conductance (TC) current driver with Trans-Impedance (TI) monitoring circuit for precise measurement of the injected current while eliminating the loading effect. The proposed IC has a low power dissipation of only3.8 mW, excluding the injection current, and offers an impressive impedance resolution of 1.9 m$1.9 mathrm{~m} Omega / sqrt{ } mathbf{H z}$. The input impedance of the IA has been increased up to 2.9 G$Omega$ at 100 Hz and 230 k$Omega$ at 1 MHz, indicating high performance over a wide range of frequencies. The effectiveness of the proposed EIT imaging IC is demonstrated by successfully reconstructing 3D images of a human body phantom using a mobile device." @default.
- W4387411191 created "2023-10-07" @default.
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- W4387411191 date "2023-09-11" @default.
- W4387411191 modified "2023-10-08" @default.
- W4387411191 title "A 3.8 mW 1.9 m Ω/√Hz Electrical Impedance Tomography Imaging with 28.4 M Ω High Input Impedance and Loading Calibration" @default.
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- W4387411191 doi "https://doi.org/10.1109/esscirc59616.2023.10268764" @default.
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