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- W4387665633 abstract "Neuromorphic computing based on spike neural networks (SNNs) exhibits great potential in reducing energy consumption in hardware systems. Resistive random-access memory (ReRAM) is regarded as a promising candidate to construct neuromorphic hardware, attributing to their high-density, nonvolatile, and compute-in-memory capability. However, the ReRAM-based neuromorphic chips are still in their infancy, cannot support multicore or with limited neuron configurability. To alleviate these problems, we propose a hybrid multicore SNN chip based on 60 K-ReRAM synapses and 480-digital neurons in the 180 nm node, achieving a synaptic density of 20K bit/mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> per core. To improve the efficiency of inter-core communication, we adopt a network-on-chip architecture with a bit character encoding strategy. In addition, an adaptive multiplier-less digital neuron is designed to support both Izhikevich and leaky integrate-and-fire models through register bit control, meeting different application scenarios. Finally, we evaluate the performance of our chip on the MNIST dataset recognition tasks, achieving 97.65% accuracy. Also, a minimum energy per synaptic operation (SOP) of 6.6 pJ in the 180 nm node is obtained, outperforming the TrueNorth’s 26 pJ in 28 nm. These results show that our design has a great potential for large-scale SNN implementations and may pave the way for designing high-efficient neuromorphic hardware with ReRAM technology." @default.
- W4387665633 created "2023-10-17" @default.
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- W4387665633 date "2023-01-01" @default.
- W4387665633 modified "2023-10-17" @default.
- W4387665633 title "Multicore Spiking Neuromorphic Chip in 180-nm with ReRAM Synapses and Digital Neurons" @default.
- W4387665633 doi "https://doi.org/10.1109/jetcas.2023.3325158" @default.
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