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- W47330819 abstract "A class of completely-pipelined VLSI architectures is defined. Two topologies are then described: leaf-connected trees and mesh-connected trees. The leaf-connected tree structure is used to construct a completely-pipelined bit-serial multiplier and a word-serial, bit-serial completely-pipelined convolver. The mesh-connected tree structure is used to implement completely-pipelined bit-parallel multiplication and completely-pipelined word-parallel, bit-parallel convolution. Layouts are described that are within log factors of asymptotic optimality. It is shown that, asymptotically, the area required for power distribution actually dominates the rest of the area for a wide class of structures. 20 references." @default.
- W47330819 created "2016-06-24" @default.
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- W47330819 date "1982-01-01" @default.
- W47330819 modified "2023-10-03" @default.
- W47330819 title "Bit-level fixed-flow architectures for signal processing" @default.
- W47330819 hasPublicationYear "1982" @default.
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