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- W47464900 abstract "본 논문에서는 Xilinx GTP 인터페이스와 DDR-2 메모리를 이용하여 개발된 고속 데이터 처리 유닛의 시험 결과를 제시하였다. 고속 데이터 처리 유닛은 1.25Gbps로 수신된 데이터를 메모리에 저장하며 이 데이터는 다시 700Mbps로 수신 저장 시스템으로 전송된다. 따라서 고속의 데이터 처리를 위해서 CPU 대신에 FPGA가 직접 메모리를 읽고 쓸 수 있도록 DDR-2 메모리 제어기를 구현 하였다. This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly." @default.
- W47464900 created "2016-06-24" @default.
- W47464900 date "2008-08-04" @default.
- W47464900 modified "2023-09-24" @default.
- W47464900 title "High Speed Data Processing Unit Development Using Xilinx GTP Interface and DDR-2 Memory" @default.
- W47464900 doi "https://doi.org/10.5139/jksas.2008.36.8.816" @default.
- W47464900 hasPublicationYear "2008" @default.
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