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- W48373497 abstract "In data transmission systems the transmission channel itself is a source of data error. Hence the need to determine the validity of transmitted and received data. Parity generation and validation is a scheme to provide single bit error detection capabilities. This application note describes how to generate and validate parity in a design using the Virtex™-II architectural features including the Block SelectRAM memory in the Virtex-II series, including the Virtex-II Pro™ devices." @default.
- W48373497 created "2016-06-24" @default.
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- W48373497 date "2002-01-01" @default.
- W48373497 modified "2023-09-24" @default.
- W48373497 title "Parity Generation and Validation for the Virtex-II Series" @default.
- W48373497 hasPublicationYear "2002" @default.
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