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- W48745973 abstract "This paper deals with systems verification techniques, using Bounded Model Checking (BMC). We present a new approach that combines BMC with symmetry reduction techniques. Our goal is to reduce the number of transition sequences, which can be handled by a SAT solver, used in the resolution of verification problems. In this paper, we generate a reduced model by exploiting the symmetry of the original model,which contains only transition sequences that represent the equivalence classes of the symmetric transition sequences. We consider the construction of a new Boolean formula that manipulates only representative transition sequences. In our technique, we present a method that combines the symmetry reduction technique with BMC for the reduction of the space and time of Model Checking." @default.
- W48745973 created "2016-06-24" @default.
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- W48745973 date "2010-07-01" @default.
- W48745973 modified "2023-09-25" @default.
- W48745973 title "SBMC : Symmetric Bounded Model Checking" @default.
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- W48745973 doi "https://doi.org/10.14236/ewic/vecos2010.9" @default.
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