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• W50376481 abstract "Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple implementation architecture. Besides existing digital control-laws, such as PID, RST, tri-mode and sliding-mode (SM), a novel digital control-law, direct control with dual-state-variable prediction (DDP control), for the buck converter is proposed based on the principle of predictive control. Compared to traditional current-mode predictive control, the predictions of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal. DDP control exhibits very high dynamic transient performances under both load variations and reference changes. Experimental results in FPGA verify the performances at switching frequency up to 4MHz. For the boost converter exhibiting more serious nonlinearity, linear PID and nonlinear SM controllers are designed and implemented in FPGA to verify the performances. A digital control requires a DPWM. Sigma-Delta DPWM is therefore a good candidate regarding the implementation complexity and performances. An idle-tone free condition for Sigma-Delta DPWM is considered to reduce the inherent tone-noise under DC-excitation compared to the classic approach. A guideline for Sigma-Delta DPWM helps to satisfy proposed condition. In addition, an 1-1 MASH Sigma-Delta DPWM with a feasible dither generation module is proposed to further restrain the idle-tone effect without deteriorating the closed-loop stability as well as to preserve a reasonable cost in hardware resources. The FPGA-based experimental results verify the performances of proposed DPWM in steady-state and transient-state. Two ASICs in 0.35µm CMOS process are implemented including the tri-mode controller for buck converter and the PID and SM controllers for the buck and boost converters respectively. The lab-scale tests are designed to lead to a power assessment model suggesting feasible applications. For the tri-mode controller, the measured power consumption is only 24.56mW/MHz when the time ratio of stand-by operation mode is 0.7. As specific power optimization strategies in RTL and system-level are applied to the latter chip, the measured power consumptions of the SM controllers for buck converter and boost converter are 4.46mW/MHz and 4.79mW/MHz respectively. The power consumption is foreseen as less than 1mW/MHz when the process scales down to nanometer technologies based on the power-scaling model. Compared to the state-of-the-art analog counterpart, the prototype ICs are proven to achieve comparable or even higher power efficiency for low-to-medium power applications with the benefit of better accuracy and better flexibility." @default.
• W50376481 created "2016-06-24" @default.
• W50376481 creator A5034995105 @default.
• W50376481 date "2012-05-07" @default.
• W50376481 modified "2023-09-23" @default.
• W50376481 title "Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées" @default.
• W50376481 hasPublicationYear "2012" @default.
• W50376481 type Work @default.
• W50376481 sameAs 50376481 @default.
• W50376481 citedByCount "0" @default.
• W50376481 crossrefType "dissertation" @default.
• W50376481 hasAuthorship W50376481A5034995105 @default.
• W50376481 hasConcept C127413603 @default.
• W50376481 hasConcept C133731056 @default.
• W50376481 hasConcept C149635348 @default.
• W50376481 hasConcept C154945302 @default.
• W50376481 hasConcept C158411068 @default.
• W50376481 hasConcept C203479927 @default.
• W50376481 hasConcept C24326235 @default.
• W50376481 hasConcept C2775924081 @default.
• W50376481 hasConcept C41008148 @default.
• W50376481 hasConcept C42935608 @default.
• W50376481 hasConcept C46362747 @default.
• W50376481 hasConcept C47116090 @default.
• W50376481 hasConcept C47446073 @default.
• W50376481 hasConcept C536315585 @default.
• W50376481 hasConcept C6557445 @default.
• W50376481 hasConcept C68754193 @default.
• W50376481 hasConcept C86803240 @default.
• W50376481 hasConceptScore W50376481C127413603 @default.
• W50376481 hasConceptScore W50376481C133731056 @default.
• W50376481 hasConceptScore W50376481C149635348 @default.
• W50376481 hasConceptScore W50376481C154945302 @default.
• W50376481 hasConceptScore W50376481C158411068 @default.
• W50376481 hasConceptScore W50376481C203479927 @default.
• W50376481 hasConceptScore W50376481C24326235 @default.
• W50376481 hasConceptScore W50376481C2775924081 @default.
• W50376481 hasConceptScore W50376481C41008148 @default.
• W50376481 hasConceptScore W50376481C42935608 @default.
• W50376481 hasConceptScore W50376481C46362747 @default.
• W50376481 hasConceptScore W50376481C47116090 @default.
• W50376481 hasConceptScore W50376481C47446073 @default.
• W50376481 hasConceptScore W50376481C536315585 @default.
• W50376481 hasConceptScore W50376481C6557445 @default.
• W50376481 hasConceptScore W50376481C68754193 @default.
• W50376481 hasConceptScore W50376481C86803240 @default.
• W50376481 hasLocation W503764811 @default.
• W50376481 hasOpenAccess W50376481 @default.
• W50376481 hasPrimaryLocation W503764811 @default.
• W50376481 isParatext "false" @default.
• W50376481 isRetracted "false" @default.
• W50376481 magId "50376481" @default.
• W50376481 workType "dissertation" @default.