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- W54110410 abstract "Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. In this paper,we first present the concept of modeling multiple valued ALU. We demonstrate that the approach allows for efficient simulation of complex multiple valued logic systems. Secondly, we show how VHDL can be used to ensure functional correctness. A generalization of binary toggle coverage for the multiple valued logic domains is presented and evaluated. As a test case, a scalable multiple valued logic arithmetic unit is modeled and experimental results for multiple valued logic toggle coverage are given." @default.
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- W54110410 date "2011-01-01" @default.
- W54110410 modified "2023-09-25" @default.
- W54110410 title "Toggle Coverage for ALU Using VHDL" @default.
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- W54110410 doi "https://doi.org/10.1007/978-3-642-18440-6_59" @default.
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