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- W574669072 abstract "Leakage power is a growing concern in modern technology nodes. In some current and emerging applications, speed performance is uncritical but many of these applications rely on untethered power making energy a primary constraint. Leakage power minimisation is therefore key to maximising energy efficiency for these applications. This thesis proposes two new leakage power minimisation techniques to improve the energy efficiency of embedded processors. The first technique, called sub-clock power gating,can be used to reduce leakage power during the active mode. The technique capitalises on the observation that there can be large combinational idle time within the clock period in low performance applications and therefore power gates it. Sub-clock power gating is the first study into the application of power gating within the clock period, and simulation results on post layout netlists using a 90nm technology library show 3.5x, 2x and 1.3x improvement in energy efficiency for three test cases: 16-bit multiplier, ARM Cortex-M0 and Event Processor at a given performance point. To reduce the energy cost associated with moving between the sleep and active mode of operation, a second technique called symmetric virtual rail clamping is proposed. Rather than shutting down completely during sleep mode, the proposed technique uses a pair of NMOS and PMOS transistors at the head and foot of the power gated logic to lower the supply voltage by 2Vth. This reduces the energy needed to recharge the supply rails and eliminates signal glitching energy cost during wake-up. Experimental results from a 65nm test chip shows application of symmetric virtual rail clamping in sub-clock power gating improves energy efficiency, extending its applicable clock frequency range by 400x. The physical layout of power gating requires dedicated techniques and this thesis proposes dRail, a new physical layout technique for power gating. Unlike the traditional voltage area approach, dRail allows both power gated and non-power gated cells to be placed together in the physical layout to reduce area and routing overheads. Results from a post layout netlist of an ARM Cortex-M0 with sub-clock power gating shows standard cell area and signal routing are improved by 3% and 19% respectively. Sub-clock power gating, symmetric virtual rail clamping and dRail are incorporated into power gating design flows and are compatible with commercial EDA tools and gate libraries." @default.
- W574669072 created "2016-06-24" @default.
- W574669072 creator A5037991791 @default.
- W574669072 date "2013-02-01" @default.
- W574669072 modified "2023-09-23" @default.
- W574669072 title "Leakage power minimisation techniques for embedded processors" @default.
- W574669072 hasPublicationYear "2013" @default.
- W574669072 type Work @default.
- W574669072 sameAs 574669072 @default.
- W574669072 citedByCount "1" @default.
- W574669072 countsByYear W5746690722020 @default.
- W574669072 crossrefType "dissertation" @default.
- W574669072 hasAuthorship W574669072A5037991791 @default.
- W574669072 hasConcept C119599485 @default.
- W574669072 hasConcept C121332964 @default.
- W574669072 hasConcept C127413603 @default.
- W574669072 hasConcept C134146338 @default.
- W574669072 hasConcept C137059387 @default.
- W574669072 hasConcept C139719470 @default.
- W574669072 hasConcept C149635348 @default.
- W574669072 hasConcept C162324750 @default.
- W574669072 hasConcept C163258240 @default.
- W574669072 hasConcept C165801399 @default.
- W574669072 hasConcept C172385210 @default.
- W574669072 hasConcept C197162436 @default.
- W574669072 hasConcept C22716491 @default.
- W574669072 hasConcept C24326235 @default.
- W574669072 hasConcept C2742236 @default.
- W574669072 hasConcept C2777042071 @default.
- W574669072 hasConcept C2780700455 @default.
- W574669072 hasConcept C2984118289 @default.
- W574669072 hasConcept C41008148 @default.
- W574669072 hasConcept C57149124 @default.
- W574669072 hasConcept C60501442 @default.
- W574669072 hasConcept C62520636 @default.
- W574669072 hasConcept C7140552 @default.
- W574669072 hasConceptScore W574669072C119599485 @default.
- W574669072 hasConceptScore W574669072C121332964 @default.
- W574669072 hasConceptScore W574669072C127413603 @default.
- W574669072 hasConceptScore W574669072C134146338 @default.
- W574669072 hasConceptScore W574669072C137059387 @default.
- W574669072 hasConceptScore W574669072C139719470 @default.
- W574669072 hasConceptScore W574669072C149635348 @default.
- W574669072 hasConceptScore W574669072C162324750 @default.
- W574669072 hasConceptScore W574669072C163258240 @default.
- W574669072 hasConceptScore W574669072C165801399 @default.
- W574669072 hasConceptScore W574669072C172385210 @default.
- W574669072 hasConceptScore W574669072C197162436 @default.
- W574669072 hasConceptScore W574669072C22716491 @default.
- W574669072 hasConceptScore W574669072C24326235 @default.
- W574669072 hasConceptScore W574669072C2742236 @default.
- W574669072 hasConceptScore W574669072C2777042071 @default.
- W574669072 hasConceptScore W574669072C2780700455 @default.
- W574669072 hasConceptScore W574669072C2984118289 @default.
- W574669072 hasConceptScore W574669072C41008148 @default.
- W574669072 hasConceptScore W574669072C57149124 @default.
- W574669072 hasConceptScore W574669072C60501442 @default.
- W574669072 hasConceptScore W574669072C62520636 @default.
- W574669072 hasConceptScore W574669072C7140552 @default.
- W574669072 hasLocation W5746690721 @default.
- W574669072 hasOpenAccess W574669072 @default.
- W574669072 hasPrimaryLocation W5746690721 @default.
- W574669072 hasRelatedWork W1589986283 @default.
- W574669072 hasRelatedWork W185249433 @default.
- W574669072 hasRelatedWork W1949070338 @default.
- W574669072 hasRelatedWork W1995006535 @default.
- W574669072 hasRelatedWork W2003272148 @default.
- W574669072 hasRelatedWork W2005728592 @default.
- W574669072 hasRelatedWork W2018816676 @default.
- W574669072 hasRelatedWork W2027062970 @default.
- W574669072 hasRelatedWork W2041557219 @default.
- W574669072 hasRelatedWork W2061180121 @default.
- W574669072 hasRelatedWork W2139875819 @default.
- W574669072 hasRelatedWork W2145376025 @default.
- W574669072 hasRelatedWork W2161621974 @default.
- W574669072 hasRelatedWork W2183933150 @default.
- W574669072 hasRelatedWork W2304720811 @default.
- W574669072 hasRelatedWork W2532126347 @default.
- W574669072 hasRelatedWork W2962853679 @default.
- W574669072 hasRelatedWork W3168700975 @default.
- W574669072 hasRelatedWork W576646735 @default.
- W574669072 hasRelatedWork W2801670045 @default.
- W574669072 isParatext "false" @default.
- W574669072 isRetracted "false" @default.
- W574669072 magId "574669072" @default.
- W574669072 workType "dissertation" @default.