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- W58596711 abstract "Abstract Recent computing-oriented FPGAs feature DSP blocksincluding small embedded multipliers. A large integermultiplier, for instance for a double-precision oating-point multiplier, consumes many of these DSP blocks.This article studies three non-standard implementationtechniques of large multipliers: the Karatsuba-Ofman al-gorithm, non-standard multiplier tiling, and specializedsquarers. They allow for large multipliers working at thepeakfrequencyoftheDSPblockswhilereducingtheDSPblock usage. Their overhead in term of logic resources,if any, is much lower than that of emulating embeddedmultipliers. Their latency overhead, if any, is very small.Completealgorithmicdescriptionsareprovided,carefullymappedonrecentXilinxandAlteradevices,andvalidatedby synthesis results. 1 Introduction A paper-and-pencil analysis of FPGA peak oating-pointperformance [8] clearly shows that DSP blocks are a rel-atively scarse resource when one wants to use them foracclerating double-precision (64-bit) oating-point appli-cations.ThisarticlepresentstechniquesreducingDSPblockus-age for large multipliers. Here, large means: any mul-tiplier that, when implemented using DSP blocks, con-sumes more than two of them, with special emphasis on" @default.
- W58596711 created "2016-06-24" @default.
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- W58596711 date "2009-08-31" @default.
- W58596711 modified "2023-09-26" @default.
- W58596711 title "Large multipliers with less DSP blocks" @default.
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