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- W592167675 abstract "In the previous chapters, we discussed in detail many facets of micro-relay technology: from device fabrication and operation to scaling and energy implications. While the previous discussion aimed to demonstrate the viability of micro-relays as an underlying technology, the next two chapters will demonstrate how micro-relays can be integrated into the existing CMOS design infrastructure. As mentioned earlier, one of the unspoken criterion for a CMOS replacement technology is that it be compatible with the extensive existing infrastructure that has been built around CMOS technology [1]. This implied requirement is largely the reason behind choosing to explore the use of a four-terminal micro-relay first, since it shares functional similarities with an MOS transistor. In particular, we will show how micro-relays can implement many of the same functional circuits as used in CMOS at a lower energy cost while using the same simulation and design tool environments." @default.
- W592167675 created "2016-06-24" @default.
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- W592167675 date "2014-09-12" @default.
- W592167675 modified "2023-09-25" @default.
- W592167675 title "Integrated Circuit Design with Micro-relays" @default.
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- W592167675 doi "https://doi.org/10.1007/978-1-4939-2128-7_6" @default.
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