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• W62333407 abstract "The design of the D0 single sided 3 chip ladder is shown in figures 1-3. The SVX II chips are mounted directly opposite the cooling channel so that they are most efficiently cooled. Outboard of the cooling channel on the ladder top side is mounted a flex hybrid of copper/kapton. which is adhered to a beryllium substrate using a two part epoxy. The beryllium substrate. aside from providing a solid mounting structure for the flex circuit. provides a thermal conduction path between the components on the hybrid which dissipate heat and the cooling channel. The thickness of the top and bottom beryllium substrates is selected based on the [expected] channel temperature. the power dissipation of the SVX II chips, the power dissipation of the hybrid passive components, and the maximum acceptable silicon temperature within the ladder. The thermal conductivity of the various materials within the ladder must be known to a fair degree of confidence in order to accurately simulate the ladder steady state cooling performance. The thermal conductivity of a number of ladder epoxy candidates was measured using a device at Lab D at Fermilab. Preliminary measurements at Lab D, using a similar setup. have been performed in order to measure the thermal conductivity of beryllium. silicon, aluminum, and other ladder materials. In order to simulate the cooling performance with confidence. prototype ladders were constructed using aluminum substrates (in place of beryllium), blank silicon, and nonfunctional prototype flex hybrid circuits. SVX II heat loads were simulated using 350 ohm strain gages which were adhered to the flex hybrid using a thin layer of epoxy. Temperatures were measured on the prototype ladders using a hand-held IR temperature probe, which has a laser focusing beam enabling simple optical focal length determination. The IR probe allows a correction to account for the surface emissivity of the material being measured. Preliminary measurements at Lab D indicate that the alloy used to construct the ladder models has a conductivity of 237 W/m-K. The assumed conductivity of the blank silicon is 149 W/m-K. Ladder prototypes with aluminum substrates were constructed using the prototype 3 chip assembly fixture at Lab D. A two dimensional cooling simulation program was written using a simultaneous equation solver. The simulation is written by dividing the 2D model into small dx and dy elements and performing an energy balance on each element based on the thermal resistance between the individual elements and their neighbors. It is otherwise known as the finite difference method. The steady state solution is obtained by solving the array of energy balance equations as a DC circuit Convective boundaries can be added on exposed elements using appropriate equations. Following is a schematic which shows the energy balance terms in each element." @default.
• W62333407 created "2016-06-24" @default.
• W62333407 creator A5061954239 @default.
• W62333407 date "1996-06-18" @default.
• W62333407 modified "2023-09-27" @default.
• W62333407 title "D0 Silicon Upgrade: Thermal Analysis of the D0 3 CHIP Single Sided Ladder" @default.
• W62333407 doi "https://doi.org/10.2172/1033284" @default.
• W62333407 hasPublicationYear "1996" @default.
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