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- W624828615 abstract "AbstractSecurity of transaction is of paramount importance in modern world of ubiquitous computing and data movement. To provide a framework of standard authenticated encryption techniques, CAESAR contest has been announced recently. Multiple entries in this contest are based on AES, which has been also, a popular choice as a primitive for authenticated encryption in the past. In this paper, we perform in-depth study of efficient hardware implementation for AES-based AEGIS-128 authenticated encryption, a prominent entry in the CAESAR contest. Through a complete study of possible throughput-area improvement techniques, we report multiple design points ranging from a high throughput of (121.07) Gbps design to a low-area implementation of (18.72) KGE, using commercial synthesis flows and 65 nm ASIC technology. We believe our results will serve as important design metric for the CAESAR contest as well as for efficient AEGIS-128 deployment.KeywordsClock CycleMaximum ThroughputParallel ArchitecturePipeline StageTechnology NodeThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves." @default.
- W624828615 created "2016-06-24" @default.
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- W624828615 date "2015-01-01" @default.
- W624828615 modified "2023-09-23" @default.
- W624828615 title "Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption" @default.
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- W624828615 doi "https://doi.org/10.1007/978-3-319-16745-9_21" @default.
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