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- W63278286 abstract "AbstractCMOS technology scaling is increasingly challenged by fundamental physics and manufacturing limits at the 22 nm node and beyond [1]. High-k/metal gate devices and strained silicon techniques help extend the lifetime of CMOS technology, but also complicate the fabrication process and increase the amount of variations. The situation is compounded by low power process, which has different device and design requirements from high performance process, and RC parasitics of scaled backend-of-the-line (BEOL) interconnect. During the pathway of scaling, process and design tradeoffs, such as those between power consumption and circuit performance, become much more complex, due to the issues in aggressively scaled CMOS technology and the implementation of new circuit design techniques. These challenges reduce the predictability of circuit performance and increase the development cycle for new products. In order to continue the design success with nanoscale CMOS, it requires an early comprehension of the technology impacts and adaptively making design decisions up front. Such a predictive capability helps identify potential issues, enables early design research, and guarantees the time to market. To accomplish this new design paradigm, it requires Predictive Technology Models (PTM) to assess performance trends, and to evaluate key modules before silicon is ready [2, 3].KeywordsRing OscillatorSRAM CellTechnology ScalingPMOS DeviceStatic Noise MarginThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves." @default.
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- W63278286 date "2011-01-01" @default.
- W63278286 modified "2023-10-18" @default.
- W63278286 title "Design Benchmark with Predictive Technology Model" @default.
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- W63278286 doi "https://doi.org/10.1007/978-1-4614-0445-3_7" @default.
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