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- W642894189 abstract "Synchronous buck converter based multiphase architectures are evaluated to
 determine whether or not the most widespread voltage regulator topology can
 meet the power delivery requirements of next generation computer
 microprocessors. According to the prognostications, the load current will rise to
 200A along with the decrease of the supply voltage to 0.5V and staggering tight
 dynamic and static load line tolerances. In view of these demands, researchers face
 serious challenges to bring forth compliant solutions that can further offer
 acceptable conversion efficiencies and minimum mainboard area occupancy.
 Among the most prominent investigation fronts are those surveying
 fundamental technology improvements aiming at making power semiconductor
 devices more effective at high switching frequency. The latter is of critical
 importance as the increase of the switching frequency is fundamentally recognized
 as the way forward to enhance power density conversion. Provided that switching
 losses must be kept low to enable the miniaturization of the filter components, one
 primary goal is to cope with semiconductor and system integration technologies
 enabling fast dynamic operation of ultra-low ON resistance power switches.
 This justifies the main focus of this thesis work, centered around a
 comprehensive analysis of the MOSFET switching behavior in the synchronous
 buck converter.
 The MOSFETs dynamic operation, far from being well describable with the
 traditional clamped inductive hard-switching mode, is strongly influenced by a
 number of frequently ignored linear and nonlinear parasitic elements that must be
 taken into account in order to fully predict real switching waveforms, understand
 their dynamics, and most importantly, identify and quantify the related
 mechanisms leading to heat generation. This will be revealed from in-depth
 investigations of the switched converter under fast switching speeds and heavy
 load.
 Recognizing the key relevance of appropriate modeling tools that support this
 task, the second focal point of the thesis aims at developing a number of suitable
 models for the switching analysis of power MOSFETs.
 Combined with a series of design guidelines and optimization procedures, these
 models form the basis of a proposed methodological approach, where numerical
 computations replace the usually enormous experimental effort to elucidate the
 most effective pathways towards reducing power losses. This gives rise to the
 concept referred to as virtual design loop, which is successfully applied to the
 development of a new power MOSFET technology offering outstanding dynamic
 and static performance characteristics. From a system perspective, the limits of the
 power density conversion will be explored for this and other emerging
 technologies that promise to open up a new paradigm in power integration
 capabilities." @default.
- W642894189 created "2016-06-24" @default.
- W642894189 creator A5013943748 @default.
- W642894189 date "2023-08-30" @default.
- W642894189 modified "2023-09-25" @default.
- W642894189 title "Prospects of voltage regulators for next generation computer microprocessors" @default.
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- W642894189 doi "https://doi.org/10.5821/dissertation-2117-94526" @default.
- W642894189 hasPublicationYear "2023" @default.
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