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- W653153512 abstract "In the deep submicron era, the power supply voltage to the logic devices should be wellwithin the bound limits. The degradation of power affects the timing closure of thechip, thus affecting the performance. In this thesis, the analysis flow used in previousstudy is modified to make it generic to all series of AVR processors. By extracting apower grid model and subjecting it to extensive simulations, the issue causing thepower degradation is analysed. Analysis results show that the cause for the firstvoltage drop is due to two factors, that is, current loads and resistive property of themetal wires. The first overshoot after voltage drop increases for wider metal wirescompared to lesser width of metal wires. Nodes of the power grid having large voltagedrop show that on-chip self inductance can no longer be ignored in designing powerdistribution networks for high frequency circuits." @default.
- W653153512 created "2016-06-24" @default.
- W653153512 creator A5072927982 @default.
- W653153512 date "2010-01-01" @default.
- W653153512 modified "2023-09-23" @default.
- W653153512 title "Power Integrity Analysis of AVR Processor" @default.
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