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• W6641605 abstract "Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide the clocks that sequence the operation of the various blocks on an ASIC chip as well as synthesize their communications. There are various types of PLLs targeting specific applications. Clock generator PLLs are capable of large frequency multiplication. They are primarily used to generate clocks for digital logic. Deskew PLLs are used to eliminate clock skew between two clock domains. They are often used in older synchronous chip-tochip IO applications. Spread spectrum PLLs slowly vary the clock frequency in order to spread a clock's electro-magnetic (EM) signature over a frequency band, thereby reducing the maximum emitted EM power at any frequency. Spread spectrum PLLs are used in many consumer products such as PCs, PDAs, etc. It is essential that PLLs be carefully specified, designed, and verified. A poorly designed or improperly used PLL can cause substantial delay in product launch or, in the worst case, total product failure. PLL architectures are generally grouped into two categories: wide-band and narrow-band. These definitions are mainly based on the voltage controlled oscillator (VCO) topologies implemented. Narrow-band PLLs generally employ the resonant characteristic of inductors and capacitors to create the VCO. They are typically used in communications applications that place stringent long-term jitter requirements on the PLL. The improved long-term jitter performance of narrowband PLLs is offset by the narrow frequency tuning range. Typically the tuning range is only 10-20% of the center frequency. A large chip area is also consumed in realizing the inductors. Furthermore, the inductance value will vary from chip to chip as a result of variations in the manufacturing process. The combination of narrow tuning range and varying inductance value necessitates extensive characterization of the VCO to ensure the target frequency range can be met across all operating PVT (process, voltage, temperature). Wide-band PLLs avoid using on chip inductors. The VCOs are commonly built as ring or relaxation oscillators, which use RC delays to establish the clock period. These PLLs have the benefit of a large frequency tuning range (Fmax/Fmin >10X), relatively small on-chip footprint, and potentially low power. However, these benefits are offset by the inferior long-term jitter characteristics of such PLLs. Hence, wide-band PLLs are seldom used in applications with stringent long-term jitter requirements." @default.
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• W6641605 date "2007-01-01" @default.
• W6641605 modified "2023-09-26" @default.
• W6641605 title "Phase-Locked Loops Demystified" @default.
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