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- W66581396 abstract "This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address these implementation challenges are discussed. As a reference, results for an HEVC decoder test chip are also presented." @default.
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- W66581396 date "2014-01-01" @default.
- W66581396 modified "2023-09-26" @default.
- W66581396 title "Decoder Hardware Architecture for HEVC" @default.
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- W66581396 doi "https://doi.org/10.1007/978-3-319-06895-4_10" @default.
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