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- W73680361 abstract "BISWAS, BARIBRATA. Modeling and Simulation of High Speed Interconnects. (Under the direction of Michael B. Steer.) A three dimensional interconnect modeling software (Layout2FastCap) was developed that takes a Layout (CIF) as its input and generates the capacitance matrix using a multipole accelerated boundary element method based numerical solver (FastCap). The software incorporates a new technique for simulating the ground plane using image method. A flow (Single Net Capacitance Extraction) was developed to handle larger layouts than that can be handled by Layout2FastCap. Experimental characterizations of the interconnects were also carried out. Results obtained from measurements were compared with the simulation results. The software Layout2FastCap is available by sending email to m.b.steer@ieee.org. Biographical Summary Baribrata Biswas was born in Ichapur, India on June 16, 1974. He received his B. Tech. degree in Electrical Engineering at the Indian Institute of Technology, Kanpur, India in May 1995. While pursuing the B. Tech. degree he worked as a summer intern at the National Center of Astrophysics, Pune, India (1993) and at the Indian Institute of Science, Bangalore, India (1994). From July 1995 to July 1996 he worked at Cadence Design Systems, Noida, India. He was admitted into the Masters Program at North Carolina State University in Fall 1996. While working towards his M. S. degree he held a Cadence Design Systems’ Fellowship and a Research Assistantship with the Electronics Research Laboratory in the Department of Electrical and Computer Engineering. In the summer of 1997 he worked as an intern at Cadence Design Systems, Cary, North Carolina. His research interests include interconnect modeling and simulation, analog and digital circuit design and solid state devices." @default.
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- W73680361 date "1999-01-01" @default.
- W73680361 modified "2023-09-27" @default.
- W73680361 title "MODELING AND SIMULATION OF HIGH SPEED INTERCONNECTS" @default.
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