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- W745688005 abstract "In this thesis, we would like to design a universal one-bit all digital phase-locked loop (ADPLL) which can be applied in the frequency range from 1 kHz to 10 MHz. The applications of this circuit include motor control, power supply design and other applications that work in the specified frequency range. We propose an efficient and reliable scheme to lock the unknown input signal within the ultra-wide frequency region. Moreover, the proposed scheme has strong noise immunity, which can work well in serious noisy environment. We divide the locking process into two parts: Acquisition Process and Tracking Process. We use the binary search to search the possible region of the input frequency in the acquisition process. We further use the tracking process to remove the frequency difference and compensate the phase error. According to our simulation results, the proposed scheme has superior performance for the designed frequency range even when SNR = 0 dB." @default.
- W745688005 created "2016-06-24" @default.
- W745688005 creator A5017633639 @default.
- W745688005 date "2010-01-01" @default.
- W745688005 modified "2023-09-28" @default.
- W745688005 title "工作於1 kHz至10 MHz並具有良好抗雜訊能力的一位元量化全數位式鎖相迴路" @default.
- W745688005 hasPublicationYear "2010" @default.
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