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• W74796267 abstract "Emerging hybrid-CMOS nanoscale devices and architectures offer greater degree of integration and performance capabilities. However, the high power densities, hard error frequency, process variations, and device wearout affect the overall system reliability. Reactive design techniques, such as redundancy, account for component failures by mitigating them to prevent system failures. These techniques incur high area and power overhead. This research focuses on exploring hybrid CMOS/Resistive RAM (RRAM) architectures that enhance the system reliability by performing computation in RRAM cache whenever CMOS logic units fail, essentially masking the area overhead of redundant logic when not in use. The proposed designs are validated using the Gem5 performance simulator and McPAT power simulator running single-core SPEC2006 benchmarks and multi-core PARSEC benchmarks. The simulation results are used to evaluate the efficacy of reliability enhancement techniques using RRAM. The average runtime when using RRAM for functional unit replacement was between ∼1.5 and ∼2.5 times longer than the baseline for a single-core architecture, ∼1.25 and ∼2 times" @default.
• W74796267 created "2016-06-24" @default.
• W74796267 creator A5001841804 @default.
• W74796267 date "2012-01-01" @default.
• W74796267 modified "2023-09-26" @default.
• W74796267 title "Reconfigurable RRAM-based computing: A Case study for reliability enhancement" @default.
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• W74796267 hasPublicationYear "2012" @default.
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