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- W75242871 abstract "We present a custom hardware system for image recognition, featuring a dimensionality reduction network and a classification stage. We use Bi-Directional PCA and Linear Discriminant Analysis for feature extraction, and classify based on Manhattan distances. Our FPGA-based implementation runs at 75MHz, consumes 157.24mW of power, and can classify a 61 ×49-pixel image in 143.7μs, with a sustained throughput of more than 7,000 classifications per second. Compared to a software implementation on a workstation, our solution achieves the same classification performance (93.3% hit rate), with more than twice the throughput and more than an order of magnitud less power." @default.
- W75242871 created "2016-06-24" @default.
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- W75242871 date "2011-01-01" @default.
- W75242871 modified "2023-10-16" @default.
- W75242871 title "Subspace-Based Face Recognition on an FPGA" @default.
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- W75242871 doi "https://doi.org/10.1007/978-3-642-23957-1_10" @default.
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