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- W76439282 abstract "With the rapid development of the programmable logic architectures and with the system performance increasingly dominated by the interconnect delay, the early work on logic synthesis for field programmable gate arrays (FPGAs) targeted at a simple array of homogeneous LUTs can no longer effectively support the rapidly evolving high-density and high-performance FPGAs. Contributions of this dissertation include the following four related aspects for FPGA synthesis: (i) technology mapping for FPGAs with embedded memory blocks (EMBs), (ii) technology mapping for heterogeneous FPGAs, (iii) timing-driven logic resynthesis, and (iv) layout-driven logic synthesis. For technology mapping for FPGAs with EMBs, we explore the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. For technology mapping for heterogeneous FPGAs, we formulate and solve the following two problems: (1) The mapping problem for heterogeneous FPGAs without bounded resources. We present the first polynomial-time delay optimal mapping algorithm that takes different delays of heterogeneous LUTs into consideration. (2) The mapping problem for heterogeneous FPGAs with bounded resources. We show that this problem is NP-hard for general networks, in contrast to the delay minimization mapping problem for heterogeneous FPGAs without bounded resources, but can be solved optimally in pseudo-polynomial time for trees. For timing-driven logic resynthesis, we propose a general methodology for iterative refinement based approaches for delay minimization. For layout-driven logic synthesis, we formulate and study the following three synthesis problems that take certain degree of layout information into consideration: (1) The mapping problem for FPGAs with nonuniform pin delays. We propose an algorithm to simultaneously perform the delay optimal LUT pin assignment and the delay optimal mapping for FPGAs with K -LUT of nonuniform pin delays in polynomial time. (2) The mapping problem for FPGAs with fast interconnections. We first show that this problem can be solved optimally in polynomial time for trees. (3) The layout-driven timing optimization problem. Targeting FPGAs with hierarchical interconnection structures, we propose a layout-driven synthesis flow to consider the effect of technology mapping and performance-driven clustering during timing-driven logic optimization. (Abstract shortened by UMI.)" @default.
- W76439282 created "2016-06-24" @default.
- W76439282 creator A5003653567 @default.
- W76439282 creator A5078536348 @default.
- W76439282 date "2000-01-01" @default.
- W76439282 modified "2023-09-24" @default.
- W76439282 title "Synthesis for high-density and high-performance fpgas" @default.
- W76439282 hasPublicationYear "2000" @default.
- W76439282 type Work @default.
- W76439282 sameAs 76439282 @default.
- W76439282 citedByCount "1" @default.
- W76439282 crossrefType "journal-article" @default.
- W76439282 hasAuthorship W76439282A5003653567 @default.
- W76439282 hasAuthorship W76439282A5078536348 @default.
- W76439282 hasConcept C11413529 @default.
- W76439282 hasConcept C131017901 @default.
- W76439282 hasConcept C134306372 @default.
- W76439282 hasConcept C149635348 @default.
- W76439282 hasConcept C157922185 @default.
- W76439282 hasConcept C173608175 @default.
- W76439282 hasConcept C206274596 @default.
- W76439282 hasConcept C2778325283 @default.
- W76439282 hasConcept C33923547 @default.
- W76439282 hasConcept C34388435 @default.
- W76439282 hasConcept C41008148 @default.
- W76439282 hasConcept C42935608 @default.
- W76439282 hasConcept C58013763 @default.
- W76439282 hasConceptScore W76439282C11413529 @default.
- W76439282 hasConceptScore W76439282C131017901 @default.
- W76439282 hasConceptScore W76439282C134306372 @default.
- W76439282 hasConceptScore W76439282C149635348 @default.
- W76439282 hasConceptScore W76439282C157922185 @default.
- W76439282 hasConceptScore W76439282C173608175 @default.
- W76439282 hasConceptScore W76439282C206274596 @default.
- W76439282 hasConceptScore W76439282C2778325283 @default.
- W76439282 hasConceptScore W76439282C33923547 @default.
- W76439282 hasConceptScore W76439282C34388435 @default.
- W76439282 hasConceptScore W76439282C41008148 @default.
- W76439282 hasConceptScore W76439282C42935608 @default.
- W76439282 hasConceptScore W76439282C58013763 @default.
- W76439282 hasLocation W764392821 @default.
- W76439282 hasOpenAccess W76439282 @default.
- W76439282 hasPrimaryLocation W764392821 @default.
- W76439282 hasRelatedWork W1967028471 @default.
- W76439282 hasRelatedWork W1968094622 @default.
- W76439282 hasRelatedWork W19874185 @default.
- W76439282 hasRelatedWork W1994323933 @default.
- W76439282 hasRelatedWork W2022898841 @default.
- W76439282 hasRelatedWork W2074149292 @default.
- W76439282 hasRelatedWork W2149239312 @default.
- W76439282 hasRelatedWork W2169142451 @default.
- W76439282 hasRelatedWork W2215330269 @default.
- W76439282 hasRelatedWork W2220804834 @default.
- W76439282 hasRelatedWork W2266600783 @default.
- W76439282 hasRelatedWork W2302276645 @default.
- W76439282 hasRelatedWork W2402143345 @default.
- W76439282 hasRelatedWork W2465311767 @default.
- W76439282 hasRelatedWork W2526889701 @default.
- W76439282 hasRelatedWork W2908839997 @default.
- W76439282 hasRelatedWork W3006926647 @default.
- W76439282 hasRelatedWork W639049436 @default.
- W76439282 hasRelatedWork W2183219250 @default.
- W76439282 hasRelatedWork W2237778701 @default.
- W76439282 isParatext "false" @default.
- W76439282 isRetracted "false" @default.
- W76439282 magId "76439282" @default.
- W76439282 workType "article" @default.