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• W765467193 abstract "Many years of research and development has shown that one valid way to solve problems of gate leakage current is that replacing conventional SiO2 gate dielectric with high-k dielectric, especially with HfO2 gate dielectrics. HfO2 gate dielectrics have been implemented at the 32nm technology node and smaller. Nevertheless, many measurement techniques must be refined, especially charge pumping techniques playing an important role in inspection of defects. Consequently, the first part mainly focuses on abnormal traps measured by the charge pumping technique for 3nm HfO2 dielectric n-MOSFETs in high gate voltage. It can be verified the abnormal traps being high-k bulk shallow traps by fitting the discharge time formula and the related formula between tunneling time and distance. To further investigate the behavior of these additional traps contributing to charge pumping current, devices with different interlayer thicknesses and different N concentrations in the TixN1-x metal gate are compared. These comparisons show that abnormal traps appear only when channel electrons inject to high-k bulk shallow traps. Subsequently, by fitting discharge formula for different tfalling time, results show that electrons escape from high-k bulk shallow traps first to the channel and then to source and drain during tfalling time. This current cannot be measured by the charge pumping technique. Subsequent measurements of NT by charge pumping technique at tbase level reveal a remainder of electrons trapped in high-k bulk shallow traps. Combining with results above, gate current is tunneling-path dominated in low Vg, and Icp detects interface trap (Nit) and “geometrical component” of Icp (Ncp,gc). On the contrary, the gate current is dominated by the Frenkel-Poole mechanism in high Vg, and Icp measures Nit, Ncp,gc, and Nhkst (high-k bulk shallow trap). The second part exhibits the extra amount of NT contributes to charge pumping current in high voltage regime in p-channel MOSFETs. Via distinguish current and current fitting, it is confirmed that initial gate current is Frenkel-Poole mechanism. Via fitting discharge formula with different temperature and related formula between tunneling time and distance, dHfO2,trap can be calculated to be 13.2A ~ 16.2A. This result is versified that extra Icp traps is actually located in the high-k bulk shallow traps in p-channel MOSFETs.The third part shows abnormal negative threshold voltage shifts under positive bias stress in input/output TiN/HfO2 n-MOSFETs using fast I-V measurement. After nine cycles of stress and recovery, Vt almost completely recovers. This result demonstrates that this process is reversible. The fast I-V double sweep measurement with insignificant gate current indicates that electrons escape from high-k bulk traps to the metal gate in Vhigh level, leading to a decrease in Vt. On the contrary, electrons inject from the metal gate to high-k bulk traps in Vbase level, causing an increase in Vt. Through curve fitting, the charge/discharge process is confirmed via the tunneling mechanism due to -1 in value in the slope. In addition, the direction of Vt shift in input/output (I/O) device is contrary to that in the standard performance device since electrons escape from high-k bulk traps to metal gate by the tunneling mechanism in I/O device rather than channel electrons injecting to bulk traps, owing to the large interlayer thickness. According to these results, the charge/discharge effect is reduced with a decrease in pre-existing high-k bulk traps, such as employing Zr doping in HfO2 dielectric device.Finally, an anomalous gate current hump is observed after dynamic negative bias stress (NBS) and negative-bias temperature-instability (NBTI) in HfxZr1-xO2 and HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. This result is attributed to hole trapping in high-k bulk traps. Fitting gate current after dynamic NBS and NBTI indicates that JFrenkel-Poole changes to JTunneling when Vg E sio2, while JTunneling changes to JFrenkel-Poole when Vg > Vt due to the influence of E high-k < E sio2. These phenomena can be attributed to the fact that the electric field must follow the formula E high-k ehigh-k = Q + Esio2e sio2. Subsequently, from Zr-undoped and Zr-doped devices after dynamic NBS, we conclude that the gate current hump requires both sufficient hole trapping and larger initial gate current. Moreover, Zr-doped devices can ameliorate dynamic NBS and NBTI. These results obey the hump generation condition JTunneling << JFrenkel-Poole." @default.
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• W765467193 date "2013-01-01" @default.
• W765467193 modified "2023-10-18" @default.
• W765467193 title "先進High-k/Metal Gate之金氧半場效電晶體 電性分析與可靠度研究" @default.
• W765467193 doi "https://doi.org/10.6842/nctu.2014.00252" @default.
• W765467193 hasPublicationYear "2013" @default.
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