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- W771094792 abstract "In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit 64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit 64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB." @default.
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- W771094792 date "2011-01-01" @default.
- W771094792 modified "2023-09-23" @default.
- W771094792 title "Hardware Design of the Synchronizer and the Demodulator of a 18000-3 PJM Mode Tag" @default.
- W771094792 hasPublicationYear "2011" @default.
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