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• W79569838 abstract "This thesis investigates timing analysis and optimization problems that arise in synchronous circuitry.We first describe algorithms for optimizing edge-triggered circuitry. Our work in this area focuses on optimization by retiming, an architectural transformation that speeds up circuitry by relocating its storage elements. A highlight of our research is an $O(Vsp{1/2}E$ lg V)-time algorithm for retiming unit-delay circuitry for maximum speed.We then move on to investigate a general class of level-clocked circuitry. We first describe algorithms that analyze the timing of level-clocked circuitry. Specifically, we give algorithms that verify the proper timing of a circuit by a given clocking scheme and analyze the sensitivity of its timing to changes in the propagation delays of its components. We also investigate clock tuning, an optimization that speeds up level-clocked circuitry by adjusting the parameters of its clocking scheme. We extend retiming to encompass level-clocked circuitry, and we describe efficient algorithms that perform retiming and tuning. We also present a retiming algorithm that minimizes the number of storage elements in level-clocked circuitry without degrading its performance. Major results of our research in this area are an O(V E + $Vsp2$lg V)-time algorithm for retiming with symmetric clocking schemes and an O(V E + $Vsp2$ lg V)-time algorithm for analyzing the sensitivity of a circuit's timing.Based on the optimization algorithms that we developed, we implemented T scIM, a versatile and efficient design automation tool for two-phase, level-clocked circuitry. The system has been implemented using the C programming language, and runs on a workstation under the UNIX environment, and it is available over the Internet.Using T scIM, we performed an empirical comparison of edge-triggered and level-clocked implementations of synchronous circuitry in terms of speed and number of storage elements. Our results show that although two-phase, level-clocked circuitry has the theoretical potential to operate faster than conventional edge-triggered circuitry, edge-triggered circuitry can often perform just as well. These empirical results indicate the special circumstances, however, in which level clocking has an advantage. Moreover, our empirical results also indicate another advantage of optimized level-clocked designs: they contain substantially fewer storage elements than edge-triggered designs that operate at the same speed. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.) (Abstract shortened by UMI.)" @default.
• W79569838 created "2016-06-24" @default.
• W79569838 creator A5041839124 @default.
• W79569838 date "1993-01-01" @default.
• W79569838 modified "2023-09-27" @default.
• W79569838 title "A Timing Analysis and Optimization System for Level-Clocked Circuitry" @default.
• W79569838 hasPublicationYear "1993" @default.
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