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- W809283117 abstract "In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling." @default.
- W809283117 created "2016-06-24" @default.
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- W809283117 date "2006-07-01" @default.
- W809283117 modified "2023-09-24" @default.
- W809283117 title "CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint" @default.
- W809283117 hasPublicationYear "2006" @default.
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