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• W811722306 abstract "In the next generation of VLSI circuits, concurrent optimizations will be essential to achieve the performance challenges. In this dissertation, we present techniques for combining traditional timing optimization techniques to achieve a superior performance.The method of buffer insertion is used in timing optimization to either increase the driving power of a path in a circuit, or to isolate large capacitive loads that lie on noncritical or less critical paths. The procedure of transistor sizing selects the sizes of transistors within a circuit to achieve a given timing specification. Traditional design techniques perform these two optimizations as independent steps during synthesis, even though they are intimately linked and performing them in alternating steps is liable to lead to suboptimal solutions. The first part of this thesis presents a new approach for unifying transistor sizing with buffer insertion. Our algorithm achieve from 5% to 49% area reduction compared with the results of a standard transistor sizing algorithm.The next part of the thesis deals with the problem of collapsing gates for technology mapping. Two new techniques are proposed. The first method, the odd-level transistor replacement (OTR) method, performs technology mapping without the restriction of a fixed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS/PTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, using the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all ISCAS'85 benchmark circuits in minutes. On average, it was found that the OTR method gave 40%, and the Static/PTL gave 50% delay reductions over SIS, with substantial area savings.Finally, we extend the technology mapping work to interleave it with placement in a single optimization. Conventional methods that perform these steps separately will not be adequate for next-generation circuits. Our approach presents an integrated solution to this problem, and shows an average of 28.19%, and a maximum of 78.42% improvement in the delay over a method that performs the two optimizations in separate steps." @default.
• W811722306 created "2016-06-24" @default.
• W811722306 creator A5047722981 @default.
• W811722306 creator A5068714995 @default.
• W811722306 date "2018-08-13" @default.
• W811722306 modified "2023-10-16" @default.
• W811722306 title "Concurrent optimization strategies for high-performance VLSI circuits" @default.
• W811722306 cites W1484483079 @default.
• W811722306 cites W1548459443 @default.
• W811722306 cites W1569550779 @default.
• W811722306 cites W186518415 @default.
• W811722306 cites W1881584521 @default.
• W811722306 cites W1965714982 @default.
• W811722306 cites W1968992562 @default.
• W811722306 cites W1982084930 @default.
• W811722306 cites W1984588379 @default.
• W811722306 cites W1984954427 @default.
• W811722306 cites W1986914234 @default.
• W811722306 cites W1990660844 @default.
• W811722306 cites W1992651809 @default.
• W811722306 cites W1996048930 @default.
• W811722306 cites W2006152335 @default.
• W811722306 cites W2010472198 @default.
• W811722306 cites W2022892565 @default.
• W811722306 cites W2024993977 @default.
• W811722306 cites W2032522597 @default.
• W811722306 cites W2035155528 @default.
• W811722306 cites W2044448266 @default.
• W811722306 cites W2048312633 @default.
• W811722306 cites W2052586721 @default.
• W811722306 cites W2055510065 @default.
• W811722306 cites W2060393099 @default.
• W811722306 cites W2065577281 @default.
• W811722306 cites W2068387533 @default.
• W811722306 cites W2069291005 @default.
• W811722306 cites W2080267935 @default.
• W811722306 cites W2086760546 @default.
• W811722306 cites W2087118030 @default.
• W811722306 cites W2089339391 @default.
• W811722306 cites W2092159784 @default.
• W811722306 cites W2100973890 @default.
• W811722306 cites W2101118951 @default.
• W811722306 cites W2106429108 @default.
• W811722306 cites W2107895817 @default.
• W811722306 cites W2108923470 @default.
• W811722306 cites W2109205632 @default.
• W811722306 cites W2110445184 @default.
• W811722306 cites W2112242460 @default.
• W811722306 cites W2112812486 @default.
• W811722306 cites W2113537658 @default.
• W811722306 cites W2113698847 @default.
• W811722306 cites W2114301751 @default.
• W811722306 cites W2114888160 @default.
• W811722306 cites W2120038452 @default.
• W811722306 cites W2128306262 @default.
• W811722306 cites W2130804120 @default.
• W811722306 cites W2131751530 @default.
• W811722306 cites W2133866802 @default.
• W811722306 cites W2134249452 @default.
• W811722306 cites W2134658528 @default.
• W811722306 cites W2135250302 @default.
• W811722306 cites W2135453964 @default.
• W811722306 cites W2143093341 @default.
• W811722306 cites W2145269393 @default.
• W811722306 cites W2146136491 @default.
• W811722306 cites W2151598461 @default.
• W811722306 cites W2154214383 @default.
• W811722306 cites W2154363431 @default.
• W811722306 cites W2155199871 @default.
• W811722306 cites W2156028445 @default.
• W811722306 cites W2160252016 @default.
• W811722306 cites W2163626738 @default.
• W811722306 cites W2164832473 @default.
• W811722306 cites W2165214930 @default.
• W811722306 cites W2166011990 @default.
• W811722306 cites W2167276231 @default.
• W811722306 cites W2168525081 @default.
• W811722306 cites W2170120409 @default.
• W811722306 cites W2427843410 @default.
• W811722306 cites W252582478 @default.
• W811722306 cites W2541364615 @default.
• W811722306 cites W2752885492 @default.
• W811722306 cites W2913046748 @default.
• W811722306 doi "https://doi.org/10.31274/rtd-180813-10782" @default.
• W811722306 hasPublicationYear "2018" @default.
• W811722306 type Work @default.
• W811722306 sameAs 811722306 @default.
• W811722306 citedByCount "0" @default.
• W811722306 crossrefType "dissertation" @default.
• W811722306 hasAuthorship W811722306A5047722981 @default.
• W811722306 hasAuthorship W811722306A5068714995 @default.
• W811722306 hasBestOaLocation W8117223061 @default.
• W811722306 hasConcept C118524514 @default.
• W811722306 hasConcept C119599485 @default.
• W811722306 hasConcept C127413603 @default.
• W811722306 hasConcept C134146338 @default.
• W811722306 hasConcept C14580979 @default.
• W811722306 hasConcept C149635348 @default.
• W811722306 hasConcept C173608175 @default.
• W811722306 hasConcept C24326235 @default.

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