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- W816609342 abstract "Reed-Solomon error correcting codes (RS codes) are widely used in communication and data storage systems to recover data from possible errors that occur during data transfer. A growing application ofRS codes is Forward Error Correction (FEC) in the Optical Net work (OTN G.709), which uses RS(255,239) to support theOTU-3 (43 .0 1 8Gbps) standard. There have been considerable efforts in the area ofRS architecture for ASIC implementa tion. However, there appears to be little reported work on efficient RS codec (encoder and decoder) for Field Programmable Gate Arrays (FPGAs), which has increasing interests in industry. This thesis investigates the implementation and designmethodology oftheRS(255,239) codec on FPGAs. A portable VHDL code is developed and synthesized for Xilinx's Virtex4 and Altera's StratixII. The FPGA architectures are analyzed and the required design methodologies are adopted to efficiently utilize the available resources. Unfortunately, due to the fixed size ofFPGA devices, the RS decoder is not only constrained by the required timing of the system, but also by the size of the targeted device. This research will facil itate the decision-making process for selecting a reconfigurable device for a RS decoder, implementing the Berlekamp-Massey Algorithm." @default.
- W816609342 created "2016-06-24" @default.
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- W816609342 date "2006-01-01" @default.
- W816609342 modified "2023-09-27" @default.
- W816609342 title "FPGA implementation of Reed Solomon codec for 40Gbps Forward Error Correction in optical networks" @default.
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