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- W830635441 abstract "This paper presents a new turbo decoding architecture for BCH(128,106,8) t=3 codes based on soft inputs and soft outputs. The design of each decoder is based on the concept of parallel decoding architecture and from the properties of product codes, this paper presents the design and complexity of three decoders able to process 2, 4 and 8 data at the same time to achieve very high data rates in decoding. To compare the performances and complexity of the decoders we have used language C for simulations, VHDL for functional simulations and Synopsys Design Compiler for the synthesis. The results obtained open the possibility future of integration on silicon of turbo decoders for high data rates (6.4 Gbits/s) with strong error correction power (minimum distance of 64, code rate of 0.8)." @default.
- W830635441 created "2016-06-24" @default.
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- W830635441 date "2003-01-01" @default.
- W830635441 modified "2023-09-26" @default.
- W830635441 title "Turbo décodage de code produit haut débit utilisant un code BCH étendu (128,106,8) t=3" @default.
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