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- W848823275 abstract "In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm." @default.
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- W848823275 date "2006-05-01" @default.
- W848823275 modified "2023-09-23" @default.
- W848823275 title "A RTL Binding Technique and Low Power Technology Mapping consider CPLD" @default.
- W848823275 hasPublicationYear "2006" @default.
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