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- W892108400 abstract "In this paper, a new architecture for fast-serial multiplier with low hardware complexity is proposed. The fast-serial multiplier operates standard basis of and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the fast-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But The traditional fast-serial architecture needs extra (t-1)m registers for achieving the t times speed. In this paper a new fast-serial multiplier without increasing the number of registers is presented." @default.
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- W892108400 title "Low Complexity Architecture for Fast-Serial Multiplier in $GF(2^m)$" @default.
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