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- W89786321 abstract "A high-density dual-port SRAM (DP-SRAM) with a 2.04 /spl mu/m/sup 2/ cell size is implemented in 90 nm CMOS technology. A dynamically-controlled column-bias scheme is presented, which reduces the active power by 64% and the stand-by current by 93%." @default.
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- W89786321 date "2004-09-28" @default.
- W89786321 modified "2023-09-30" @default.
- W89786321 title "A 90nm dual-port SRAM with 2.04 μm/sup 2/ 8T-thin cell using dynamically-controlled column bias scheme" @default.
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- W89786321 doi "https://doi.org/10.1109/isscc.2004.1332817" @default.
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